1. Field of the Invention
The present invention relates to a protection component, and more particularly to a protection component designed to protect telephone lines.
2. Discussion of the Related Art
European patent application EP-A-0,687,051 filed by the applicant describes a circuit for protecting a telephone line interface and specific embodiments of the circuit in the form of a monolithic component. FIG. 1 of the present patent application is a copy of FIG. 4 of the above-mentioned application and represents an element of the circuit including two head-to-tail connected thyristors Th1 and Th2, respectively having a cathode gate and an anode gate. Thyristors Th1 and Th2 are connected between a line AB and a reference terminal G. The gates are interconnected to point B. A common terminal of thyristors Th1 and Th2 is connected to point A, a resistor Rd being connected between points A and B. The other common terminal of thyristors Th1 and Th2 is connected to the reference terminal G. A Zener diode Z1 connected between terminals B and G causes, when avalanching, thyristor Th1 to trigger. A Zener diode Z2 connected between terminals A and G causes, when avalanching, thyristor Th2 to trigger. When the current between terminals A and B exceeds a predetermined threshold, either one of thyristors Th1 and Th2 is triggered by its gate.
Thus, in the circuits of FIG. 1, depending on its biasing, either one of thyristors Th1 and Th2 becomes conductive if the current in resistor Rd exceeds a predetermined threshold or if the voltage on line AB exceeds the avalanche voltage of diode Z1 or Z2.
FIG. 2 of the present patent application is a copy of FIG. 7 of the afore-mentioned application and constitutes an embodiment of the circuit of FIG. 1. An indication of the locations of elements Th1, Th2, Z1 and Z2 of FIG. 1 has been added in FIG. 2.
When designing and realizing the invention related to the afore-mentioned application, the applicant noted that one of the main difficulties to be solved was to obtain similar sensitivities for the gate triggering of thyristors Th1 and Th2 and to obtain suitable hold currents. Thus, various means were indicated in the afore-mentioned application to solve this problem.
However, during the implementation of the circuit, the applicant noted that, although the triggering of thyristor Th1 due to the avalanching of the Zener diode Z1 raises no particular problem, the sensitivity of the triggering of thyristor Th2 due to the flow of current through resistor Rd should be further improved. More particularly, the triggering was too slow (duration longer than 1 .mu.s). Efforts of optimizing the location of the component (see FIGS. 8A-8B of European patent application 0,687,051) have been unsuccessful. Thus, when an overcurrent with a particularly sharp edge (for example, a standardized wave 0.5/700 .mu.s of a 30-A intensity) occurs on line AB, the thyristor Th2 becomes conductive after a slight delay and, during this delay, the protection component transmits the 30-A peak current, which can damage the integrated circuit that is to be protected.